A. Field of Invention
The present invention pertains generally to computer bus systems and more specifically to computer bus systems which allow host computers, otherwise referred to as initiators, to communicate with various peripheral storage devices, such as disc drives and tape drives, which are otherwise referred to as targets.
B. Description of Background
Computer bus systems control the flow of information between the various components that are connected to the system. This information can comprise data, commands, and messages. Computer bus systems normally utilize a standardized protocol which sets forth a predetermined set of rules for controlling the flow of information on the bus. One such protocol is the Small Computer Systems Interface (SCSI) protocol which has been adopted widely in the personal computing industry. The SCSI protocol has a very complete set of rules for controlling the flow of information on the bus. Each component, i.e., each initiator and each target, has a controller which functions as an interface unit between the component (i.e., the target or initiator) and the bus. The present invention pertains to a system that can be implemented as a initiator controller on a SCSI bus system.
Prior art initiator controllers, especially for SCSI protocol busses, operate with numerous interrupts of the initiator microprocessor. For example, some prior art initiator controllers require interrupts to prepare for "Selection", to prepare for "Message-Out" and to prepare for a "Command" when the initiator selects a target and sends a command, to prepare for a "Message-In" when a target sends a disconnect signal, to prepare for "Message-In" when a target reselects, to "Prepare for Data" when a first target transfers data in or out, to prepare for a "Message-In" when a target sends "Save Pointers" and "Disconnect" messages, to prepare for "Status" and "Message-In" when a target sends "Status" and "Command Complete." It is possible for all of these interrupts to be handled in an automated fashion, without interrupting the microprocessor and holding the bus idle while the microprocessor processes the information. Elimination of interrupts, in this fashion, would greatly decrease the overall response time of the computer system, especially for virtual memory systems where frequent access must be made to stored data.
A significant problem that is encountered in minimizing Initiator Processor interrupts for an Initiator Controller is the result of the fact that the Target Controller controls the bus phases after selection by the Initiator. As a result, the Initiator must be ready for various occurrences to take place after the target has been selected. The specific case which is somewhat programmatical is the situation where a first Target (Target A) decides to stop receiving data (Write data) from the Initiator, releases the bus, and second Target (Target B) reselects and starts sending data (Read data) to the Initiator. In that instance, Write data that was being sent by the Initiator Controller to Target A is left resident in a first-in first-out (FIFO) device in the Initiator Controller and Read data being received by the FIFO of the Initiator Controller from Target B overwrites the Write data that was left in the FIFO to be sent to Target A. In some instances, the Write data that was lost in this manner can be retrieved by backing up the tape or re-addressing the disc system to read the data again when Target A reselects. However, this may take a considerable amount of time, and, consequently, substantially increase the overall response time of the system. Moreover, in many instances such as the use of certain streaming tape drives, such as the HP88780 streaming tape drive, the data cannot be reaccessed and is lost.
An alternative to reaccessing the data on the tape or disc is to produce a processor interrupt whenever Target A disconnects from the bus while receiving Write data and Target B reselects. However, whenever Target B reselects in this situation it does not always send data but may, instead, send Status or Command signals to the Initiator. If Command or Status signals were to be sent by Target B in this instance, processor interrupts would not be required to prevent the overwriting of data in the FIFO and, hence, an unnecessary processor interrupt would be introduced into the system.